1. Field of the Invention
The present invention relates to a semiconductor storage apparatus including memory cells that need refresh operation.
2. Related Art
As for the conventional DRAM cell consisting of one transistor and one capacitor including a trench capacitor or a stacked capacitor, there is a concern that its fabrication may become difficult as it becomes finer. As a candidate for a future DRAM memory cell, a new memory cell FBC (Floating Body Cell) is proposed (see Japanese Patent Application Laid-Open Nos. 2003-68877 and 2002-246571). In the FBC, majority carriers are formed in a floating body of an FET (Field Effect Transistor) formed on SOI (Silicon on Insulator) or the like, to store information.
In the FBC, an element unit for storing one bit information is formed of only one MISFET (Metal Insulator Semiconductor Field Effect Transistor). Therefore, the occupation area of one cell is small, and storage elements having a large capacity can be formed in a limited silicon area. It is considered that the FBC can contribute to an increase of the storage capacity.
The principle of writing and reading for an FBC formed on PD-SOI (Partially Depleted-SOI) can be described as follows by taking an N-type MISFET as an example. A state of “1” is defined as a state in which there are a larger number of holes. On the contrary, a state in which the number of holes is smaller is defined as “0.”
The MISFET includes an nFET formed on SOI. Its source is connected to GND (0 V) and its drain is connected to a bit line (BL), whereas its gate is connected to a word line (WL). Its body is electrically floating.
For writing “1” into the FBC, the transistor is operated in the saturation state. For example, the word line WL is biased to 1.5 V and the bit line BL is biased to 1.5 V. In such a state, a large number of electron-hole pairs are generated near the drain by impact ionization. Among them, electrons are absorbed to the drain terminal. However, holes are stored in the body having a low potential. The body voltage arrives at a balanced state in which a current generating holes by impact ionization balances a forward current of a p-n junction between the body and the source. The body voltage is approximately 0.7 V.
A method of writing data “0” will now be described. For writing “0,” the bit line BL is lowered to a negative voltage. For example, the bit line BL is lowered to −1.5 V. As a result of this operation, a p-region in the body and an n-region connected to the bit line BL are greatly forward-biased. Therefore, most of the holes stored in the body are emitted into the n-region. A resultant state in which the number of holes has decreased is the “0” state. As for the data reading, distinguishing between “1” and “0” is conducted by setting the word line WL to, for example, 1.5 V and the bit line BL to a voltage as low as, for example, 0.2 V, operating the transistor in a linear region, and detecting a current difference by use of an effect (body effect) that a threshold voltage (Vth) of the transistor differs depending upon a difference in the number of holes stored in the body. The reason why the bit line voltage is set to a voltage as low as 0.2 V in this example at the time of reading is as follows: if the bit line voltage is made high and the transistor is biased to the saturation state, then there is a concern that data that should be read as “0” may be regarded as “1” because of impact ionization and “0” may not be detected correctly.
The FBC stores information relating to the difference of the number of majority carriers. While data is retained, the word line is set to a negative value with the source of the grounded cell. In both the “1” state and the “0” state, since the potential of the body is thus set to negative values by using capacitive coupling between the word line and the body, p-n junction between the body and the source and p-n junction between the body and the drain are reverse-biased. In this way, a current flowing between the body and the source and a current flowing between the body and drain are held down to low values.
Since there is a slight reverse bias current across each PN junction, however, holes flow into the body little by little. Since the gate is set to a negative potential as compared with the drain, there is also a flow of holes to the body caused by GIDL (Gate Induced Drain Leakage). Since the data “1” is the state in which the number of holes is originally large, therefore, it is sufficient to replenish holes which overflow when the body potential is raised to a positive value in ordinary read/write operation. As for data “0”, however, refresh operation for bailing holes over a certain fixed period becomes necessary.
As compared with the conventional 1T (Transistor)-1C (Capacitor) type DRAM cell, the FBC is small in P-N junction area because the SOI substrate is used and the leak current can be held down to a comparatively small value. However, the capacitance for storing electric charge is less than 1 fF in the FBC whereas it is several tens fF in the conventional 1T-1C type DRAM cell. Therefore, it is inevitable that the data retaining time becomes shorter than that in the DRAM. Therefore, there is a drawback that the frequency of refreshing becomes high and the external access period for conducting the read/write operation is limited by that amount.
In a VSRAM (Virtually Static RAM) including conventional 1T-1C type cells, if read/write operation is conducted from the outside and a competition with the internal refresh operation occurs, the read/write operation must be kept waiting until the refresh operation is completed (see K. Sawada et al., “A 30-uA Data-Retention Pseudostatic RAM with Virtually Static RAM Mode”, IEEE J. Solid-State Circuits, vol. 23). The reason is because the 1T-1C cell is a destructive read-out cell. In other words, once the WL is activated and data begins to be read out, cell data is destroyed if interruption occurs without amplifying the data and completing the rewrite operation. This results in a drawback that the random access time and the random write time are prolonged to twice or more if the VSRAM is composed by using the 1T-1C type DRAM.